Semiconductor integrated circuits, as well as the design, manufacture, and operation of such circuits, are well known in the art. Common to such circuits is an epitaxially grown single crystal film in which various regions of different conductivity type are interconnected by multiple layers of patterned electrically conducting material.
A variety of electrically conducting material is available for implementing the layers. Gold, copper, aluminum, Polycrystalline Silicon (or "polysilicon"), and various metal alloys, for example, are all suitable to some extent. On the other hand, each has its drawbacks as is well known in the art.
In large scale integration (LSI)-metal-oxide-semiconductor (MOS)-field effect transistor (FET) technology, polysilicon has become the standard material for the conducting layer closest to the epitaxial film. Typically, the polysilicon layer is a first layer separated from a second electrically conducting overlay by an insulating layer typically of silicon dioxide.
Polysilicon exhibits relatively high resistivity and the lengths of polysilicon paths are limited as a consequence. For example, various functional areas in an integrated circuit chip cannot be interconnected together directly by polysilicon. Rather, the connections from each area are brought out to aluminum bus bars formed from the second overlay. Similarly, LSI high speed circuits require high conductivity input-output lines. The requirement results in the exclusion of polysilicon as a material for such use. Aluminum power lines are needed and this often requires aluminum bonding pads within the chip. The additional aluminum areas, are, essentially, wasted space and parallel aluminum conductors yield problems.
Copending application Ser. No. 974,378 for Levinstein, Murarka, and Sinha, filed Dec. 29, 1978 discloses the high conductivities of silicides used with a thin layer of polysilicon. The method for fabrication described therein involved depositing a layer of Ti or Ta on a polysilicon layer. The resulting structure was then sintered at about 900 degrees C. to form TiSi.sub.2 or TaSi.sub.2. The excess silicon from the polysilicon layer allowed a later oxidation to SiO.sub.2.
In order to improve resolution of patterns in layers of material on chips with increasingly higher packing densities, and therefore, increasingly narrower apertures, it is advantageous to reduce the thickness of the layers as well. One route to this goal would be the elimination of the high-resistance polysilicon layer completely. However, in the above-mentioned application of Levinstein, Murarka and Sinha, it is stated that the polysilicon layer is necessary as a source of silicon for the reduction of the metal to silicide and for the subsequent oxidation to form SiO.sub.2. It is also stated that in the absence of the polysilicon, the silicide forming layer will react with the underlying gate oxide to form an undesirable oxide overlay which cannot be etched. A problem thus exists as to the realization of increasingly thinner layers in which patterns are formed for realizing increasingly higher packing density devices.